1. Field of the Invention
This invention relates to an electrical pulse timing deskew circuit with independently variable rising and falling pulse edge delays, and particularly to a deskew circuit for Emitter Coupled Logic (ECL) circuits used in automatic test equipment.
2. Description of the Prior Art
Test systems for integrated circuits (IC's) must determine, among other things, whether the IC being tested meets timing specifications. For this purpose it is desirable to synchronously apply pulses to the input pins of an IC, and detect the resultant output signals. It is not generally possible to build multiple test system circuits each having little enough pulse timing variation to produce signal patterns with all pulse edges from all circuits precisely aligned across the IC input pins. Accordingly, the time difference, or "skew" of each pulse relative to a reference time, must be measured and corrected to assure that the IC is properly tested and the results correctly interpreted. Although in some applications it is necessary to adjust only the leading edge or only the trailing edge, both edges must be independently adjustable to provide patterns to test all aspects of many IC's.
One prior art technique for deskewing signals employed adjustable capacitors in the signal path. This technique required manual adjustment of each capacitor, and was therefore undesirably time consuming. Another technique, disclosed in copending commonly assigned U.S. patent application Ser. No. 365,829 filed Apr. 5, 1982, uses a variable delay line having multiple taps. The signal delay varies in proportion to the path length to the selected tap. Because the tapped delay line is relatively costly, there is a need for a more economical deskew circuit.